Automated Design Error Debugging of Digital VLSI Circuits
نویسندگان
چکیده
Abstract As the complexity and scope of VLSI designs continue to grow, fault detection processes in pre-silicon stage have become crucial guaranteeing reliability IC design. Most algorithms can be solved by transforming them into a satisfiability (SAT) problem decipherable SAT solvers. However, solvers consume significant computational time, as result search space explosion problem. This ever- increasing amount data handled via machine learning techniques known deep algorithms. In this paper, we propose new approach utilizing for (FD) combinational sequential circuits type stuck-at-faults. The goal proposed semi-supervised FD model is avoid taking advantage unsupervised supervised processes. First, process attempts extract underlying concepts using Deep sparse autoencoder. Then, tends describe rules classification that are applied reduced features detecting different stuck-at faults within circuits. proposes good performance terms running time about 187 × compared other algorithm based on addition, it common classical models such Decision Tree (DT), Random Forest (RF) Gradient Boosting (GB) classifiers, validation accuracy. results show maximum accuracy feature extraction at 99.93%, autoencoder For circuits, stacked presents 99.95% average delivers around 99.6% from ISCAS’85 99.8% ISCAS’89 benchmarks. Moreover, has achieved 1.7x, DT classifier 1.6x, RF GB occurred eight digital Furthermore, outperforms models, Radial Basis Function Network (RBFN), achieving 97.8%
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ژورنال
عنوان ژورنال: Journal of Electronic Testing
سال: 2022
ISSN: ['0923-8174', '1573-0727']
DOI: https://doi.org/10.1007/s10836-022-06020-z